High-Speed Counter Definition Counters

Inputs/Outputs Operands Data Types
HSC Constant (0,1,2,3,4, or 5) BYTE
MODE Constant (0,1,2,3,4,5,6,7,8,9,10, or 11) BYTE

Memory Ranges ENO Errors Instruction Support for S7-200 CPUs SIMATIC/International Mnemonics
The High-Speed Counter Definition (HDEF) instruction assigns a MODE to the referenced high-speed counter (HSC).

PLC 221 and PLC 222 do not support HSC1 and HSC2.

Only one HDEF box may be used per counter.

Error Conditions that Set ENO = 0:

SM4.3 (run-time), 0003 (input point conflict), 0004 (illegal instruction in interrupt), 000A (HSC redefinition)

Defining a High-Speed Counter

High-Speed Counter Mode and Input Assignments

Setting Current and Preset Values for HSCs

Selecting the Active State and 1x/ 4X Mode