Interrupt Event Priority Table for CPU 21x Series

Event Interrupt Priority Priority Supported by:
No. Description Group in Group

210

212

214

215

216


8 Port 0: Rcv character Comm. 0  
9 Port 0: Xmt complete (Highest) 0*  
23 Port 0: Rcv msg complete   0*      
24 Port 1: Rcv msg complete   1        
25 Port 1: Rcv character   1*        
26 Port 1: Xmt complete   1*        
0 Rising edge, I0.0** Discrete 0
2 Rising edge, I0.1 (Middle) 1    
4 Rising edge, I0.2   2    
6 Rising edge, I0.3   3    
1 Falling edge, I0.0**   4  
3 Falling edge, I0.1   5    
5 Falling edge, I0.2   6    
7 Falling edge, I0.3   7    
12 HSC0 CV=PV**   0  
13 HSC1 CV=PV   8    
14 HSC1 direction changed   9    
15 HSC1 external reset   10    
16 HSC2 CV=PV   11    
17 HSC2 direction changed   12    
18 HSC2 external reset   13    
19 PLS0 pulse count   14    
20 PLS1 pulse count   15    
10 Timed interrupt 0 Timed 0  
11 Timed interrupt 1 (Lowest) 1    
21 Timer T32 CT=PT interrupt   2      
22 Timer T96 CT=PT interrupt   3      

* Because communication is inherently half-duplex, both transmit and receive are the same priority.

** If event 12 (HSC0 CV=PV) is attached to an interrupt, then neither event 0 nor event 1 can be attached to interrupts. Likewise, if either event 0 or 1 is attached to an interrupt, then event 12 cannot be attached to an interrupt.

Interrupts are serviced on a first-come first-served basis within their respective priority assignments. Thus, only one user interrupt service routine shall ever be active at any point in time. If a timed interrupt is under service, neither a subsequent discrete bit interrupt nor a communication interrupt shall pre-empt the timed interrupt routine. The interrupts are queued for later processing.