|EVNT||Constant CPU 221/ 222: 0-12, 19-23, 27-33
CPU 224: 0-23; 27-33
CPU 226 / 226XM: 0-33
|Memory Ranges||ENO||Errors||Instruction Support for S7-200 CPUs||SIMATIC/International Mnemonics|
|The Attach Interrupt (ATCH) instruction associates an interrupt event (EVNT) with an interrupt routine number (INT), and enables the interrupt event.
Error Conditions that Set ENO = 0:
SM4.3 (run-time), 0002 (conflicting assignments of inputs to an HSC).
Interrupts are serviced by the PLC on a first-come first-served basis according to the assigned event priority group. Only one user interrupt can be active. Interrupts that occur while another interrupt is active are queued for later processing.
If more interrupts occur than the queue can handle, SM queue overflow status bits are set. These bits are reset when the queue is empty, and control is returned to the main program.
Read these bits from the interrupt routine in order to determine if you have a queue overflow. You can have the following number of interrupts in queue before an overflow occurs.
|Queue Type||CPU 221||CPU 222||CPU 224||CPU 226/226XM|
Queue Overflow (Interrupts)
Interrupt Event Time Intervals
Interrupt Event Priority Table