SCR (Sequence Control Relay) Usage

Controlling Program Flow with SCR Segments

The main program in an S7-200 PLC consists of instructions that are executed sequentially once per scan of the PLC. For many applications it may be appropriate to logically divide the main program into a series of operational steps, that mirror steps within a controlled process (for example, a series of machine operations).

One way to logically divide a program into multiple steps is to use SCR segments. By using SCR segments it is possible to divide your program into a single stream of sequential steps, or into multiple streams that can be active simultaneously. It is possible to have a single stream conditionally diverge into multiple streams, and to have multiple streams conditionally re-converge into a single stream.

Understanding SCR Instructions

·The LSCR (STL) or SCR (LAD/FBD) instructions load the SCR and logic stacks with the value of the S bit referenced by the instruction. The entire SCR segment is energized or de-energized by the resulting value of the SCR stack. The LSCR instruction defines the beginning of an SCR segment.

·The SCRE instruction defines the end of an SCR segment. Code that appears after an SCRE (and before another LSCR) is not part of an SCR segment.

·All logic between the LSCR (STL) instruction and the SCRE instruction make up the SCR segment and are dependent on the value of the S stack for execution. Logic between the SCRE instruction and the next LSCR instruction are not part of an SCR segment, and will be executed on every scan of the program.

·The SCRT instruction sets an S bit to enable another SCR segment and also resets the S bit that was loaded to enable the current SCR segment. By executing the SCRT, the program will logically transition to the next step.

Restrictions for using SCRs follow:

·You cannot use the same S bit in more than one routine. For example, if you use S0.1 in the main program, do not use it in the subroutine.

·You cannot use the JMP and LBL instructions in an SCR segment. This means that jumps into, within, or out of an SCR segment are not allowed. You can use jump and label instructions to jump around SCR segments.

·You cannot use the FOR, NEXT, and END instructions in an SCR segment.

Types of Logical Control Flow

Sequential Control

A process with a well-defined sequence of steps is easy to model with SCR segments. For example, consider a cyclical process, with 3 steps, that should return to the first step when the third has completed.

The STL code to accomplish the above example would consist of the following:

NETWORK

LSCR "State_L"// Beginning of SCR segment for State L

NETWORK

//…. Any code within the Segment

NETWORK

LD I0. 0// If some transition logic.

SCRT "State_M"// enable State M, and disable State L.

NETWORK

SCRE// End of SCR segment for State L

NETWORK

LSCR "State_M"// Beginning of SCR segment for State M

NETWORK

//…. Any code within the Segment

NETWORK

LD I0. 1// If some transition logic.

SCRT "State_N"// enable State N, and disable State M.

NETWORK

SCRE// End of SCR segment for State M

NETWORK

LSCR "State_N"// Beginning of SCR segment for State N

NETWORK

//…. Any code within the Segment

NETWORK

LD I0. 2// If some transition logic.

SCRT "State_L"// enable State L, and disable State N.

NETWORK

SCRE// End of SCR segment for State N.

Divergence Control

In many applications, it may be appropriate for a single stream of sequential states to diverge into two or more simultaneous streams. When a stream of control diverges into multiple streams, all outgoing streams must be activated simultaneously, as shown in the following diagram:

The STL code to accomplish the above example would consist of the following:

NETWORK

LSCR "State_L"// Beginning of SCR segment for State L

NETWORK

//…. Any code within the Segment

NETWORK

LD I0. 0// If I0.0

SCRT "State_M"// enable State M,

SCRT "State_N"// and enable State N.

NETWORK

SCRE// End of SCR segment for State L

Convergence Control

A similar situation arises when two or more streams of sequential states must be merged into a single stream. When multiple streams merge into a single stream, they are said to converge. When streams converge, all incoming streams must be complete before the next state is executed The following diagram illustrates convergence:

The code to control convergent streams is slightly more complex. To ensure that all incoming streams have completed, it is necessary to implement a network that will be executed on every scan (that is, it is not part of any SCR segment), to check for the completion of all incoming streams. The following STL code implements convergence of two incoming streams:

NETWORK

LSCR “State_L”// Beginning of SCR segment for State L

NETWORK

//…Any code within the segment

NETWORK

LD V100.5// If V100.5, then Transition out of State L

SCRT“State_Lx”// into State Lx

NETWORK

SCRE// End of SCR segment for State L

NETWORK

LSCR“State_M”// Beginning of SCR segment for State M

NETWORK

//…Any code within the segment

NETWORK

LD V34.5// If V34.5, then Transition out of State M

SCRT“State_Mx”// into State Mx

NETWORK

SCRE// End of SCR segment for State M

NETWORK

LD“State_Lx”// If State L complete

A“State_Mx”//and State M complete

S“State_N”, 1// Set S bit to enable State N

R“State_Lx”, 1// Reset S bit to disable State Lx

R“State_Mx”, 1// Reset S bit to disable State Mx