Set Dominant Bistable Bit Logic

Inputs/Outputs Operands Data Types
S1, R (LAD) Power Flow BOOL
S1, R (FBD) I, Q, M, SM, T, C, V, S, L, Power Flow BOOL
OUT (LAD) Power Flow BOOL
OUT (FBD) I, Q, M, SM, T, C, V, S, L, Power Flow BOOL
xxx I, Q, M, V, S BOOL

Memory Ranges ENO Errors Instruction Support for S7-200 CPUs SIMATIC/International Mnemonics
The Set Dominant Bistable (SR) is a latch where the set dominates. If the set (S1) and reset (R) signals are both true, the output (OUT) will be true.

The xxx function block parameter specifies the Boolean parameter that is set or reset. The optional output reflects the signal state of the xxx parameter.